1. Field of the Invention
The present invention relates to passive voltage contrast tests and, more particularly, to a method of reducing the time required to perform a passive voltage contrast test.
2. Description of the Related Art
A passive voltage contrast test is a test that is commonly performed on semiconductor devices that have failed. The test determines whether any of the circuit nodes in an area of interest of a layer of interest have a grounded or floating electrical state, with respect to a grounded substrate, that is other than expected. In other words, a passive voltage contrast test identifies the circuit nodes which are grounded, but which should be floating, and which are floating, but which should be grounded, thereby identifying any points of failure.
To perform the test, a semiconductor device is lapped down in a conventional fashion to expose a layer, such as a contact/via layer where the exposed contacts/vias of the layer represent the circuit nodes, or a metal layer where the exposed metal regions of the layer represent the circuit nodes. For example, a passive voltage contrast test can be performed on a via layer or a metal layer where all of the overlying layers have been removed, or a contact layer where all of the layers down to and including the metal-1 layer have been removed.
After the die has been lapped down, the die is imaged using, for example, a focused ion beam (FIB) system or a scanning electron microscope (SEM) system. In a SEM system, the substrate of the die is placed on a grounded stub, and scanned with an electron beam. The scanning electron beam electrically charges the non-grounded circuit nodes which, in turn, allow a passive voltage contrast image of the area of interest of the layer of interest to be generated. In the image, nodes that are tied to the substrate typically have a white center region, while nodes that are floating, such as contacts that are connected to a polysilicon gate, typically have a black center region.
FIG. 1 is a diagram that illustrates a prior-art passive voltage contrast image 100. As shown in FIG. 1, image 100 has a number of dots 110 that include white dots 110W which represent circuit nodes (e.g., contacts) that are connected to ground, and a number of black dots 110B which represent circuit nodes that are floating.
Once a passive voltage contrast image, such as image 100, has been formed, a failure analyst next compares a circuit layout with the image to identify each dot in the image, and the expected state (grounded or floating) of each dot. After each dot has been identified, the actual state (grounded or floating) of each dot as indicated in the image is compared with the expected state as indicated by the circuit layout to determine whether the actual state matches the expected state.
Although passive voltage contrast tests provide a powerful approach to detecting faults, one serious drawback to the approach is that the dots in a passive voltage contrast image are typically examined by hand. As a result, the examination of the dots in the image becomes a tremendously labor intensive project. For example, given a failure location, there could be anywhere from 2 to 50 different nets to examine.
One approach to this problem is to test both a known good die and an unknown die. A failure analyst then compares the passive voltage contrast image from the known good die with the passive voltage contrast image from the unknown die. Thus, rather than identifying each dot in the image and determining whether the dot has the expected value, only the dots in the two images which fail to match need be identified.
Although this approach reduces the time required to identify the dots in a passive voltage contrast image, there is a need for additional approaches.
As noted, FIGS. 2, 4, 5, and 6 are flow charts illustrating methods according to embodiments of the present invention. The techniques illustrated in these figures may be performed sequentially, in parallel or in an order other than that which is described. It should be appreciated that not all of the techniques described are required to be performed, that additional techniques may be added, and that some of the illustrated techniques may be substituted with other techniques.